Minimizing Power Consumption in Combinational Logic Circuits by Reducing Switching Activity. University of Thi-Qar Journal for Engineering Sciences, [S. l.], v. 2, n. 1, p. 118–125, 2011. DOI: 10.31663/utjes.v2i1.181. Disponível em: http://jeng.utq.edu.iq/index.php/main/article/view/181.. Acesso em: 30 apr. 2024.