Minimizing Power Consumption in Combinational Logic Circuits by Reducing Switching Activity
DOI:
https://doi.org/10.31663/Keywords:
switching activity, low-power consumption, combinational circuits, CMOS circuit, K-mapAbstract
The aim of the present paper is to investigate the minimization of the power
consumption in combinational circuits by reducing the switching activity. A synthesis
approach based on an iterative procedure that compares the minterms consequently, eliminate
the complementary variables, then ORing all the terms in one simplified equation is
introduced . The results show that about 10% reduction in switching activity has been
obtained by using this method if it is compared with the normal optimal solution obtained
from K-map method
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Copyright (c) 2011 The Author(s), under exclusive license to the University of Thi-Qar
This work is licensed under a Creative Commons Attribution 4.0 International License.