Minimizing Power Consumption in Combinational Logic Circuits by Reducing Switching Activity

Authors

  • Nahla D. Habeeb Electrical Engineering dept. ,College of Engineering, University of Mustansirya, Baghadad,Iraq

DOI:

https://doi.org/10.31663/utjes.v2i1.181

Keywords:

switching activity, low-power consumption, combinational circuits, CMOS circuit, K-map

Abstract

The aim of the present paper is to investigate the minimization of the power consumption in combinational circuits by reducing the switching activity. A synthesis approach based on an iterative procedure that compares the minterms consequently, eliminate the complementary variables, then ORing all the terms in one simplified equation is introduced . The results show that about 10% reduction in switching activity has been obtained by using this method if it is compared with the normal optimal solution obtained from K-map method.

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Published

2011-03-01

Issue

Vol. 2 No. 1 (2011)

Section

Articles

License

Copyright (c) 2011 The Author(s), under exclusive license to the University of Thi-Qar

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

Minimizing Power Consumption in Combinational Logic Circuits by Reducing Switching Activity. (2011). University of Thi-Qar Journal for Engineering Sciences, 2(1), 118-125. https://doi.org/10.31663/utjes.v2i1.181